| Connectivity/Interface |
Name |
Description |
Download |
SVRCS |
MIPI (Mobile Industry Processor Interface) CSI2 Receiver. |
|
CCMIPI |
MIPI D-PHY |
|
HDMIrx_IP_V9T065 |
Dual Port HDMI 1.3 Receiver IP 65nm, TSMC. |
|
HDMIrx_IP_V9S13 |
Dual Port HDMI 1.3 Receiver IP .13um, SMIC. |
|
HDMIrx_IP_V9T18 |
Dual Port HDMI 1.3 Receiver IP 180nm, TSMC |
|
HDMIrx_IP_V9T13 |
Dual Port HDMI 1.3 Receiver IP 130nm, TSMC |
|
HDMIrx_IP_V7T09 |
Single Port HDMI 1.3 Receiver IP 90nm, TSMC |
|
HDMIrx_IP_V3T065 |
HDMI 1.3 Transmitter IP 65nm, TSMC |
|
EP936 |
HDMI 1.3 Transmitter IP 180nm , X-fab |
|
PHY_IP |
USB2.0 PHY, UTMI for device 0.25um, TSMC, VIS. |
|
PHYIPV1 |
USB2.0 PHY, UTMI for device and host 0.25um, TSMC, VIS. |
|
OTGPHYIP |
USB2.0 OTG PHY, UTMI+ level 1 0.25um, TSMC, VIS.
|
|
OTGPHY3IP18 |
USB2.0 OTG PHY, UTMI+ level 3 0.18um, TSMC/SMIC/UMC. |
|
UBT6800 |
USB 2.0 Device PHY. |
|
UBT6900 |
USB 2.0 Host PHY. |
|
UBT6920 |
USB 2.0 OTG PHY. |
|
UBT6100 |
USB 1.1 PHY. |
|
UBH6600 |
USB 2.0 Hub PHY, 1 upstream/4 downstream. |
|
UBT6920TIA |
It is comprised of both USB1.1 and USB2.0 transceivers. |
|
SPCUSB20 |
USB 2.0 Device Core. |
|
SPCUSB20HOST |
USB 2.0 Host Controller. |
|
SPCOTG20 |
USB 2.0 OTG IP Core. |
|
SPCHUBTT |
USB 2.0 HUB TT Core. |
|
USB3.0 Host Controller |
USB 3.0 Host Controller. |
|
W1394 |
IEEE 1394 has a comprehensive portfolio of IEEE 1394 IPs that consist of Link Layer and Physical Layer cores along with all associated software for the latest 1394a and 1394b standards. |
|
SED425 |
Compatible with SATAII 1.2~3.25Gbps, PCIe and SONET |
|
SPCPCIX1 |
PCI-X Core |
|
EC310 |
Certified PCI Express compliance with PCI-SIG. |
|
EP423 |
The 64-bit PCI-X host bridge core is optimized to operate in both PCI mode and PCI-X mode. |
|
PC423 |
The 64-bit PCI-X master/target core is optimized to operate in both PCI mode and PCI-X mode. |
|
EC220 |
The 32-bit PCI bus Master/target supports. Up to 133Mbyte/sec at 33Mhz and 266Mbyte/sec at 66Mhz.Responds to standard PCI configuration access. |
|
EC125 |
The 32-bit PCI bus target contains functions as a target to all PCI bus accesses. |
|
EP430 |
The 32-bit PCI host bridge support. Zero wait state and user inserted wait state burst data transfer.Up to 133Mbyte/sec at 33Mhz and 266Mbyte/sec at 66Mhz. |
|
EP454 |
Fully supports PCI specification 2.2 to 3.0 protocol and AHB bus protocol, transfer size, burst size and response types. |
|
EP440 |
The PCI-to-PCI Bridge and fully supports PCI bus specification 2.2 and PCI bridge specification 1.1. |
|
EC150 |
The PCI-to-ISA bridge which supports 16-bit and 8-bit data transfer, memory and IO transfers on ISA bus. |
|
EC300 |
The PCI bus arbiter two to eight bus masters.Bus parking.Single cycle request-to-grant turn around time.Quiet cycle during master switch.Master time-out. |
|
EP140 |
Supports AHB bus interface to the ARM CPU and data width of 8, 16 and 32 bits.Dual read buffers to process CPU read.Multiple bus slave is supported by Ready signal input and outputs. |
|
EP240 |
Supports AHB bus interface to the ARM CPU.User interface designed for high speed access to any slave devices on the AMBA AHB Bus.Supports all slave device responses: OKAY, RETRY, SPLIT and ERROR. |
|
EP504 |
This controller provides high speed SDRAM data access to the ARM CPU and user-defined logic. |
|
EP534 |
This controller provides high speed DDR SDRAM data access to the ARM CPU and user-defined logic. |
|
EP454 |
AHB to PCI Host Bridge.Fully supports PCI specification 2.2 to 3.0 protocol.Supports AHB burst transfers up to 16 data words. |
|
EP246 |
Multiple independent DMA channels with direct AHB bus interface.DMA transfers between AHB memory devices and I/O ports. |
|
EP201 |
This PowerPC bus interface core is designed to initiate read/write data transfer on the PowerPC CPU host bus.Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260. |
|
EP100 |
This PowerPC bus interface core is designed as a target for CPU or other bus master access. |
|
EP433/434 |
This PowerPC IP core allows the CPU to access the PCI bus recources and to configure the PCI bus under software control. |
|
EP300 |
Fully supports PowerPC™ 60x bus protocol, include PowerPC 603, 604, 740, 750 and 8260.Supports up to eight PowerPC bus masters with unlimited slave device support. |
|
EP150 |
MIPS SysAD Bus Slave.Supports 64-bit MIPs CPU bus through the SysAD bus interface.Supports single and burst access from CPU.Dispatches CPU request to SDRAM controller, FLASH controller, PCI, user interface, and system control registers. |
|
EP450 |
SysAD Bus to PCI Host Bridge.Fully supports PCI specification 2.1 and 2.2 protocol.Supports SysAD bus protocol.Supports SysAD bus burst transfers up to 64 bytes. |
|
EP155 |
MIPS EC Interface Bus Slave.Compliant to the EC Interface of the MIPS CPU.Supports MIPS64 5K and MIPS32 4K processor core family. |
|
EP505 |
This controller provides high speed SDRAM data access to the MIPS CPU and user-defined logic. |
|
EP455 |
EC Interface to PCI Host Bridge.Fully supports PCI specification 2.1 and 2.2 protocol.Supports EC Interface burst transfers up to 64 bytes. |
|
