20Kc |
MIPS64 20Kc - Dual issue 64-bit MIPS Processor Core, 7 stages pipepine, 32KB 4-way instruction cache, 32KB 4-way instruction cache, Balanced integer and floating-point performance of 1370 DMIPS and 2.4 GFLOPS (peak) on 533MHz TSMC Hardcore with the ability to scale to over 1 GHz in future process technologies. |
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4Kc |
MIPS32 4Kc Synthesizable 32 bit MIPS Processor Core. Configurable 2,4,8,12, 16 KB instruction & data cache size and set associative (1,2,3,4). 5 stages pipeline. 32-entry TLB MMU with programable 4KB-to-4MB page size. Featured with MDU & Fast MAC. 1.3 DMIPS / MHz. |
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